The present invention is related in general to the field of semiconductor devices and processes and more specifically to integrated circuits structure, fabrication and operation as they relate to data storage an chip identification.
Cutting through a thin film of metal or doped polycrystalline semiconductor by laser pulses has been practiced for many years as a method of irreversibly opening electrical fuses. A well-known example is the repair of memory integrated circuits (IC) based on available redundant building blocks. Another example, the reading of electrical data stored in an information unit associated with ICs, is described in U.S. patent application Ser. No. 60/094,097, filed on Jul. 24, 1998 (Gelsomini et al., xe2x80x9cIntegrated Circuit Wireless Taggingxe2x80x9d).
The method, however, of opening metal fuses by laser pulses is expensive. It requires extra process steps and expensive laser equipment in device fabrication. Furthermore, the silicon real estate needed for the layout of the metal fuses is substantial. Most important, opening fuses by laser pulses is very expensive for writing information. The semiconductor industry has, therefore, considered the approach of anti-fuses. It is a circuit element that is normally open circuited until it is programmed, at which point the anti-fuse assumes a relatively low resistance. Anti-fuses are commonly used to selectively enable certain features of ICs and to perform repairs by replacing defective portions with redundant circuits.
Conventional anti-fuses are similar in construction to capacitors; they have a pair of conductive plates separated from each other by a dielectric such as oxide or nitride. The dielectric is changed into a conductive regime by applying a differential voltage between the plates that is sufficient to break down the dielectric, thereby allowing for electrical connection between the plates. Typically this high programming voltage is applied to the IC externally. It is a disadvantage of anti-fuses that the programmed resistance may vary over a considerable range and is often far higher than desired. Further, the magnitude of the programming voltage that can be applied to the anti-fuses is severely limited by the presence of other circuitry.
An example for using anti-fuses is given in U.S. Pat. No. 4,590,589, issued on May 20, 1986 (Gerzberg, xe2x80x9cElectrically Programmable Read-only Memoryxe2x80x9d). The antifuse described is normally nonconductive until a sufficient voltage is applied across the anti-fuse to lower the resistance thereof and become conductive. The anti-fuse can comprise a portion of an n-type silicon substrate with an implanted region formed in a surface region by the introduction of p-type ions. The implanted ions disrupt the crystalline structure of the substrate and the disrupted crystalline structure increases the resistance between the implanted region and the substrate. By applying a sufficient voltage across the implanted region, the crystalline state of the region is reinstated and the resistance thereof drops appreciably. After removing the voltage, the disrupted state is restored only partially or insufficiently for a repeat operation.
The anti-fuse as described above has been applied in U.S. Pat. No. 5,799,080, issued on Aug. 25, 1998 (Padmanabhan et al., xe2x80x9cSemiconductor Chip Having Identification/Encryption Codexe2x80x9d) to provide a code mechanism in an IC for identifying the IC or for enabling the IC. However, the code is readily accessible for interrogation and enablement only once. Alternatively, the code can be reprogrammed by use of an electrically erasable field effect transistor.
U.S. Pat. No. 5,844,298, issued on Dec. 1, 1998 (Smith et al., xe2x80x9cMethod and Apparatus for Programming Anti-Fusesxe2x80x9d) describes a programming circuit for anti-fuses fabricated in the same IC. Relatively large (positive) programming voltages are applied from the outside so that relatively elaborate circuitry is needed to protect gate oxide layers in MOSFETs of the IC from damage.
An urgent need has therefore arisen to conceive a concept for a low-cost, yet high performance method of encoding anti-fuses in ICs to allow chip identification. Preferably, this method should be based on fundamental design concepts flexible enough to be applied for different semiconductor product families and a wide spectrum of design and assembly variations. No extra process steps should be required. The method should not only meet high electrical and information performance requirements, but should also achieve improvements towards the goals of enhanced process yields and device reliability. Preferably, these innovations should be accomplished using the installed equipment base so that no investment in new manufacturing machines is needed.
According to the present invention, an information write-register embedded in an integrated circuit is made of a plurality of gate-controlled MOS transistors or capacitors having a gate insulator geometry locally susceptible to electrical conductivity upon applying overstress voltage pulses, whereby information can be permanently encoded into the write-register. In order to supply the pulses selectively to the component gates, a plurality of level shifters, also embedded in the integrated circuit, outputs the pulses on the basis of inputs received from stored data and enable commands.
The present invention is related to semiconductor integrated circuits (ICs) of any kind, especially those having high density and high value. These ICs can be found in many semiconductor device families such as processors, digital and analog devices, memory and logic devices, high frequency and high power devices, specifically in large area chip categories. The invention offers an inexpensive way to permanently write into, and store, a coded individual identification as well as manufacturing and engineering data. Examples include wafer lot number, wafer number, chip location on the wafer, test results, electrical and functional characteristics, and so on. The writing can be performed at the wafer level, or after packaging of the unit.
It is an aspect of the invention to offer desirable features to both the manufacturer and the user at no extra cost:
Data writing and reading: Individual wafer level engineering data can be stored and then retrieved at any time, even after chip assembly and packaging. Parametric and functional performance data measured at wafer level can be compared to final test data after assemblyxe2x80x94a necessity in manufacturing science for cost-conscious process development.
Anti-theft coding: Permanently recording the producer, date of production, country of origin, user ID, is a significant crime deterrent.
ISO 9000 requirements: Permanent chip identification is desired in qualification.
Military requirements: Permanent identification of manufacturer and country of origin.
User""s data: Inputs for personal interest of the user.
Another aspect of the invention is to require no extra process steps and no extra equipment, and also to operate at high speed so that no extra cost is added to the manufacturing.
Another aspect of the invention is to be conservative with real estate requirements, especially to require not more silicon area for the MOS transistors to be programmed than for standard metal fuses.
Another aspect of the invention is to provide reading of the information by sensing (with the use of sense amplifiers) the electrical status of the MOS transistors and loading their logic content into a shift register. The different electrical characteristics of the MOS transistors which have been programmed can be detected by sensing the voltage of a specific line of the information write-register.
Another aspect of the invention is to provide means for identifying and handling redundancy of rows or columns, and for selecting certain circuit portions over others (so-called xe2x80x9ctrimmingxe2x80x9d). This capability is based on the fact that the electrical status of MOS transistor insulators is equivalent to the electrical status of conventional metal or polysilicon fuses.
Another aspect of the present invention is to design the information write-register so that he information can be encoded in a data bank while the chip is still in wafer form, as well as after its singulation. This aspect is achieved by providing a plurality of electrical anti-fuses in the data bank, which can be irreversibly transformed into the conductive state by applying overstress voltage pulses.
Another aspect of the invention is to design the information write-register, level shifters, write-control logic, and read-control logic such that their fabrication is flexible and can be adopted to the most commonly used and accepted IC fabrication processes.
These aspects have been achieved by the teachings of the invention concerning design concepts and process flows suitable for mass production. Various modifications have been successfully employed to satisfy different selections of product design and processes.
In the first embodiment of the invention, the circuit of a chip identifier module is described, consisting of write-control and write-control logic including information register, and read-control and read-control logic. MOS transistors are used having gate insulators made of silicon dioxide in a thickness range from about 5 to 10 nm. These oxides can be locally transformed into the conductive state by pulses in the range from 6 to 10 V and 10 to 50 xcexcs duration.
In a variation of this embodiment, field transistors are used having the field oxide similar to the gate oxide in the MOS transistor embodiment.
In another variation, capacitors are used having electrically conductive terminals and an intermediate insulating layer of characteristics similar to the MOS gate oxides in the MOS transistor embodiment.
In the second embodiment of the invention, the circuit of a redundancy or trimming module is described, consisting of write-control and write-control logic, and rows/columns redundancy logic, or trimming logic.
The technical advances represented by the invention, as well as the aspects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.